The present invention relates to programmable logic devices (PLDs), and in particularly, to programming of PLDs using programming pulses having the width dynamically varying during a programming procedure.
A programmable logic device (PLD) is a digital integrated circuit capable of being programmed to provide a variety of different logic functions. A PLD generally includes AND gates, OR gates, and input/output buffers, and may use on-chip fuses, UV erasable programmable read-only memory (EPROM) arrays, or electrically erasable programmable read-only memory (EEPROM) arrays to programmably create data paths and logic functions that are specific to the user""s design. Erasable programmable memory arrays allow the desired functionality of the PLD to be re-programmed many times. This programmability makes a PLD a flexible and powerful tool for a large number of unique applications. For example, in-system programmable logic devices can be field programmed, i.e. programmed in their operating environment without removal from the system where they are deployed.
A complex PLD may include multiple function blocks for performing any one of a variety of logic functions. The logic function performed by a particular logic block is defined by data stored in its associated configuration memory cells. Configuring or programming the PLD is achieved by a programming device that writes configuration data into configuration memory cells.
Verification is required after programming to ensure that the memory cells have been properly programmed and that the PLD is functional to the design specification. Verification of a PLD involves a combination of functional testing, simulation and timing analysis.
Programming of PLDs may be performed using automatic testing equipment or tester so as to achieve advantages of programming, verifying the programming and testing the PLDs on a single piece of equipment and within the operating environment of the PLD. The tester generally includes computerized control circuitry, driver and receiver channels, and connectors for connecting electrical pins of a PLD to be programmed to the driver and receiver channels.
An automatic tester produces a test pattern defining particular functions to be programmed in the PLD. The test pattern specifies programming signals, test signals and expected output signals as a set of test vectors. Test vectors generally provided in digital form indicate a data value, timing and format of each signal during a test cycle. For example, the data value of a signal during a particular test cycle may be specified as either high or low level, the timing of the signal may be defined as a delay relative to the beginning of the test cycle, and the format may indicate that the signal is to be either applied to or observed at a particular pin of the PLD. The tester generally detects defects in programming of a PLD whenever the output signal received from the PLD do not match the expected output signal.
As thousands or even millions of test vectors are required to program a complex PLD, a test pattern programming process may take substantial amount of time. Therefore, it would be desirable to provide a method of test pattern programming that would reduce the time of programming.
The present invention offers a novel method of dynamically programming a programmable logic device (PLD). The method involves programming a required pattern, such as a test pattern, into the PLD using a programming pulse signal having a first pulse width. Then, the PLD programming is verified. If the PLD programming is found to be improper, the pulse width of the programming pulse signal is automatically adjusted to a second pulse width greater than the first pulse width. Thereafter, the required pattern is again programmed into the PLD using the programming pulse signal having the second pulse width.
The programming of a next pattern into the PLD may be initiated using the programming signal having the first pulse width. If the PLD programming is incorrect, the programming is repeated using the second pulse width.
In a preferred embodiment of the invention, the first pulse width may be the minimum pulse width of the programming signal sufficient to perform programming of the PLD. The minimum value of the pulse width may be determined experimentally.
In accordance with another aspect of the invention, the system for programming a PLD comprises a programming device configured for programming the PLD using a programming signal having a first pulse width, and for automatically adjusting the programming signal to program the PLD using the programming signal having the second pulse width greater than the first pulse width, if the PLD programming performed using the first pulse width is incorrect.
Preferably, the programming device includes a tester for programming a test pattern into the PLD and verifying the PLD programming.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.